The utilisation of silicon photonics technology, leveraging on its compatibility with current complementary-metal-oxide-semiconductor (CMOS) production processes, is extending from current low to medium volume applications, for example in parallel optical transceivers, to optical multi-chip modules (OMCM) in new high bandwidth hardware platforms. Advantageously, OMCMs enable electronic and optical chips to be integrated within a single module, with low power consumption, high processing capacity and low footprint. It is expected that these OMCMs may be used for example in high capacity switches for data centres and in large IP routers, as the increase in traffic demand pushes telecommunication equipment vendors to continually increase the bandwidth density of their switching equipment, as well as to reduce the cost and power consumption of the equipment.
A first OMCM technology which may deployed may be an OMCM comprising only a single 3D interposer. The OMCM may comprise a silicon photonics integrated circuit (SOI) chip (performing input/output functions) with an electronic integrated circuit (EIC) on top of it. The EIC may perform signal processing functions, and be connected, with very short wires (2-3 cm) to one or a few high capacity electronic processing ASIC/FPGAs. However, to increase the bandwidth density of the modules, it is expected that more than one 3D interposer may be integrated in a single OMCM.
However, a problem then arises of how to effectively interconnect the respective silicon photonics integrated chips using optical links, whilst avoiding waveguide crossing, and taking into account that the dimensions of a single optical interposer are currently limited to about 3 cm×3 cm owing to the size of the photo-mask reticule used to produce CMOS chips. This problem will increase as it is desired to integrate more and more chips onto an OMCM.